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Flash memory

Flash in embedded devices is a really hot topic – there are quite some questions which should be asked before choosing the “right” flash memory type. Often the wrong decision turns out to backfire – I experienced this in several projects and companies.
 
Questions which should get asked for evaluating possible flash chips and types are:
 
Those questions should be dealt with quite carefully when evaluating the right type of flash for a project.
 
Since to most of the above questions there aren’t really simple answers but implications to each other and of course each solution its very own advantages and disadvantages, I’ll try to illustrate some scenarios instead.
 

Erase blocks and erase cycles

 
Flash storage consists of so-called “erase blocks” (just called blocks from now on). Its size highly depend on the kind of flash (NOR/NAND) and the flash total size.
 
Usually NOR flash has much greater blocks than NAND flash – typical block sizes are e.g. 64KB for a 4MB NOR flash, 64KB for a 256MB NAND flash, 128KB for a 512MB NAND flash.
When flash (especially NAND flash) got bigger and bigger in storage size, pages and later sub-pages got introduced.
 
NAND flash consists of erase blocks which might consist of pages which might consist of sub-pages.
 
Though pages and sub-pages can be directly addressed for reading, only whole erase-blocks can be – guess what? – erased.
 
NAND flash also may contain an ‘out of band (OOB) area’ which usually is a fraction of the block or – if any – page size. This is dedicated for meta information (like information about bad blocks, ECC data, erase counters, etc.) and not supposed to be used for your actual data payload.
Flash storage needs to be addressed ‘by block’ for writing. Blocks can only be ‘erased’ for certain times, till they get corrupted and unusable (10.000 – 100.000 times are typical values).
 
Usual conclusion of above is, flash storage can be read but not written byte wise – to write to flash, you need to erase the whole block before. This is not totally wrong, but misleading since simplified.
Flash storage cells by default have the state “erased” (which matches the logical bit ’1′). Once a bit got flipped to ’0′ you can only get it back to ’1′ by erasing the entire block.
 
Even though you can indeed only address the flash “per erase block” for writing – and you have to erase (and therewith write the whole erase block) when intended to flip a bit from ’0′ to ’1′ – that doesn’t mean every write operation needs a prior block erase.
Bits can be flipped from ’1′ to ’0′ but only an entire block can be switched  (erased) in order to get bits within back to ’1′.
 
Considering an (in this example unrealistic small) erase block contains ’1111 1110′ and you want to change it to, let’s say, ’1110 1111′, you have to:
1) erase the whole block, so it will be ’1111 1111′
2) flip the 4th byte down to ’0′
But if we e.g. want to turn ’1111 1110′ into ’1010 0110′ we just flip the 2nd, 4th and and 5th bit of the block. That way we don’t need to erase the whole block before, because no bit within the block needs to be changed from ’0′ to ’1′.
That way, due to clever write handling of the flash, not every write operation within erase blocks imply erasing the block before.
 
Taking this into account might significantly enhance the lifetime of your flash (especially SLC NAND, MLC requires some even more sophisticated methods), as blocks can only be erased a certain number of times.
It might also allow you to take cheaper flash (with less guaranteed erase cycles).
 
Also you should make sure, that you don’t keep a majority of erase blocks untouched, while others get erased thousands of times.
To avoid this, you usually some kind of ‘wear leveling’. That means, you keep track of how many times blocks got erased, and – if possible – relocate data on blocks, which gets changed often, to blocks which didn’t get erased that often.
To get wear leveling done properly, you need to have certain amount of blocks in spare to be able to rotate the blocks and relocate the actual data properly.

Hardware vs. Software

Both techniques can significantly improve the lifetime of your flash, however require quite some sophisticated algorithms to get a reasonable advantage over not using them.
Bare flash doesn’t deal with those issues. There is controller hardware taking care of that (e.g. in higher-class memory cards / USB sticks), but it usually sucks. If possible, do it in software.
Using e.g. Linux to drive your flash, offers quite some possibilities here (looking at file-systems).

NAND vs. NOR

NOR blocks compared to those of NAND, in relation to the total storage size of the flash, are quite big – which means:

Bad blocks

Bad blocks and how they’re dealt with decides whether you can use your flash in the end as normal storage or end up in debugging nightmares, caused by weird device failures which might result of improper bad block handling of your flash.
 
A bad block is considered an erase block, which shouldn’t be used anymore because it doesn’t always store data as intended due to bit flips. This means, parts of the block can’t be erased (flipped back to ’1′ anymore, parts “float” and can’t be get into a well-defined state anymore, etc.). Blocks only can be erased certain amount of times, until they get corrupted and therewith ‘bad’. Once you encounter a probably bad block, it should be marked as bad immediately and never ever be used again.
 
Marking a bad block means: Adding this bad block to a table of bad blocks (which is mostly settled at the end of the flash). Since this table sit within blocks on the flash, which might get bad as well, this table is usually redundant.
 
Bad blocks happen, especially on NAND flash. Even never used NAND flash, right from the factory, might contain bad blocks. Because of that, NAND flash manufacturers ship their flash with “pre-installed” information about which blocks are bad from the beginning. Unfortunately, how this information is stored on the flash, is vendor / product specific. Another common area to store this kind of information the OOB area (if existing) of the flash.
 
This also means, flash of the very some vendor and product, will have a different amount of usable blocks. This is a fact you have to deal with – don’t be too tight in your calculation, you’re going to need space in spare as replacement for bad blocks!

Hardware vs. Software

There are actually NAND chips available doing bad block management by their own. Although I never  used them myself, what I read it sounds quite nice. Most bare flash however doesn’t deal with bad blocks. There might be pre-installed information about bad blocks from the beginning, there might be not. And if there is, the format is what the vendor chose to be the format.
That means, if using a flash controller dealing with bad blocks for you, it needs to be able to read and write the type of format those information are stored in. It needs to be aware about whether the flash has an OOB-areas or not and how they’re organized.
 
There is quite some sophisticated and flexible flash controller hardware out there, but again: if possible, do it in software. There is quite good and proven code for that available.

NAND vs. NOR

NOR flash is way more predictable than NAND flash. NAND flash blocks might get bad whenever they want (humidity, temperature, whatever..).
Reading NAND flash stresses it as well – yes, reading NAND flash causes bad blocks! Although this doesn’t happen as often as due to write operations (and far less on SLC than on MLC flash), it happens and you better deal with it!
The number of expected erase cycles is mentioned in the data-sheets of NAND flashes. The number of read cycles isn’t. However it’s usually something around 10 to 100 times the erase cycles.
Imagine you want to boot from your NAND flash, and the boot-loader – which doesn’t deal yet with bad blocks – sits within blocks which react unpredictable / become bad.. a nightmare!
That’s why it’s common now, that the first few blocks of NAND flash are guaranteed to be safe for the first N erase cycles. Make sure your boot-loader fits into those safe blocks!

SwitchSmart!

The “radio controlled power sockets”-project finally got its very own name and project site:

SwitchSmart!

Several improvements happened since my last post about this project:

PostgreSQL – altering table name does not update references to its primary key and sequence automatically

During a setup of multiple PostgreSQL instances, replicating content via the replication framework Slony-I, I had to manually create the very same SQL schema to every Postgres node – as Slony just replicates the payload data and not the actual SQL schemas.

I was creating tables like this on every node:

CREATE TABLE x (
id             SERIAL PRIMARY KEY,
content   VARCHAR(255) DEFAULT NULL
);

but decided after half of having those nodes I already configured to rename the table from ‘x‘ to ‘y‘ using the ‘ALTER TABLE‘ command

ALTER TABLE x RENAME TO y;

and continued creating the schemas on the remaining nodes with the following command:

CREATE TABLE y (
id             SERIAL PRIMARY KEY,
content   VARCHAR(255) DEFAULT NULL
);

After finally having provided the schema to all nodes I started the replication daemons and got thrown errors from half of the nodes that replication doesn’t work properly since the schema doesn’t match the one on the master replication server:

CESTERROR  remoteWorkerThread_1: “select “_db”.setAddTable_int(1, 3, ‘”public”.”y”‘, ‘x_pkey’, ‘Table public.y with primary key’); ” PGRES_FATAL_ERROR ERROR:  Slony-I: setAddTable_int(): table “public”.”y” has no index x_pkey

All of the non-working nodes were those, I first created the table x on and later renamed it to y, instead of just directly creating table y like I did on the others.

Looking at the global table definitions – including the automatically co-created sequence – you can see that the table did get renamed, but the sequence didn’t:

Table y directly created:

postgres=# d
List of relations
Schema |      Name      |   Type   |  Owner
——–+—————-+———-+———-
public | y              | table    | postgres
public | y_id_seq       | sequence | postgres
(4 rows)

Table x created and altered to be named y:

postgres=# d
List of relations
Schema |      Name      |   Type   |  Owner
——–+—————-+———-+———-
public | y              | table    | postgres
public | x_id_seq       | sequence | postgres
(4 rows)

That normally doesn’t cause any trouble, since the reference of table y (formerly x) to the sequence x_id_seq is still valid. However since replication requires the very exact same schema on every node this actually is causing trouble. However that’s not the error mentioned in the error message above, which is referring to the primary key.

Diff’ing the actual schemas shows up more differences:

                                  Table “public.y”
Column  |          Type          |                   Modifiers
———+————————+————————————————
- id      | integer                | not null default nextval(‘x_id_seq‘::regclass)
+ id      | integer                | not null default nextval(‘y_id_seq‘::regclass)
content | character varying(255) | default NULL::character varying
Indexes:
-    “x_pkey” PRIMARY KEY, btree (id)
+    “y_pkey” PRIMARY KEY, btree (id)

The reference to the sequence and and name of the reference to the value of the primary key were NOT updated by altering the table name to match again. This separation of table-name and references might be a feature, however I find it hard to imagine a use-case where it makes sense using the sequence and/or primary key of another table. UPDATE: I just got told that it indeed might make sense sharing one sequence among several tables.

Also sequence and primary key were created inside / co-created by the ‘CREATE TABLE‘ statement, so at least I’d find it more consistent if both would be always reference by this table, by means of the table they got originally created with.

Looking for information, hints or documentation about this behaviour wasn’t fruitful as well.

So personally I’d really like to really see those reference updated – by changing the tables name - automatically.  I’d like to see at least a NOTICE that primary key and sequence are still haveing the name of / are referring to it’s old values and need to be updated / re-created to match again.

Conclusion: Make sure – when altering table names in Postgres – references to primary key and sequence are getting updated as well – manually! Primary key and sequence are NOT tied together with the table they got created with!

LinuxInput devices (in Qt embedded) – take care!

I’m currently working on an embedded project based on Linux which involves a graphical user interface based on Qt.

In our case Qt accesses framebuffer as well as the LinuxInput devices directly – there is no further layer (DirectFB, Xorg, Wayland, etc.) in between.

In this quite common scenario I noticed that Qt is treating the LinuxInput devices in a quite counterintuitive way which may lead into severe security problems.
The embedded device we are using in this particular project has a keyboard which to the userland is exposed as LinuxInput device.

Everything worked quite well, however our Qt application crashed once due to a programming error (our fault) and I was shown the underlying UNIX console which reflected every single keystroke I did inside the Qt application – all typing input within the Qt application also got passed to other applications / underlying shells!

An exposed root shell to the active TTY – possibly hidden by the GUI – is therewith also capturing all input. Since almost all linux (embedded) distributions are exposing login prompts / shells to all TTYs by default, this scenario is far from being unlikely.

My expected behavior would have been: the Qt application is opening the LinuxInput devices exclusively, so that only the Qt application receives data from the input devices.

After some research and asking around I got pointed to the EVIOCGRAB IOCTL implemented in the LinuxInput subsystem.

As stated in $(LINUX_KERNEL)/include/input/linux.h:

@grab: input handle that currently has the device grabbed (via
EVIOCGRAB ioctl). When a handle grabs a device it becomes sole
recipient for all input events coming from the device

This means: When opening LinuxInput devices they’re not grabbed, they’re not opened exclusively by default.

Okay, I got it :)

So let’s just find the magic option / command which tells Qt to set up an EVIOCGRAB with an appropriate argument on the going-to-be-used LinuxInput device. Since I didn’t find any documentation I grep’ed through the Qt source:

> ~/src/qt.git$ git grep EVIOCGRAB
> ~/src/qt.git$

nothing… so I took a closer look into how Qt implemented support for LinuxInput devices (src/gui/embedded/qkbdlinuxinput_qws.cpp) – still nothing…

So I implemented support for telling Qt to open LinuxInput devices exclusively by optionally passing an ‘grab’-argument to the LinuxInput drivers inside Qt.

And here it is – a patch which adds support for passing another parameter named ‘grab’ to the LinuxInput device driver of Qt – to specify whether the device should be opened exclusively (grabbed) or not.

https://dev.openwrt.org/browser/packages/Xorg/lib/qt4/patches/500-allow-device-grabbing.patch?rev=26780

Conclusion: Take care when using Qt and its LinuxInput drivers – all input might be received and used by other applications as well – including shells running on TTYs.

 

UPDATE: The patch finally git committed and went upstream. Grabbing can now be configured since Qt version 4.8 (http://www.qt.gitorious.org/qt/qt/commit/947aaa79b05adec527c7500e36766c7ff19f118d/diffs)

RFM12 – kernel patches

Since I got asked several times about the pin mappings and wirings between the rfm12 modules and GPIOs of the devices providing them (in my case the Netgear WGT634U router / the Qi NanoNote) I’d like to try making some things clearer:

In Linux the use of buses is tried to get as abstracted as possible – the idea is that the actual boards (or call it whatever you like as devices, platforms etc) define and expose the capability of buses and its properties.

In our case the rfm12 kernel module requires the availability of an SPI bus – it doesn’t matter how it is implemented (native SPI bus, SPI over GPIOs or any other way of implementation). The client module – the kernel module implementing an driver for the actual rfm12 hardware – simply doesn’t care and doesn’t need to know about that.

That’s the reason why the actual rfm12 code doesn’t contain any GPIO <-> rfm12 hardware mappings – the rfm12 code is just using an existing and otherwise exposed SPI bus.

The actual wiring / mapping and setup of the SPI bus is done within the platform / board / device code, which is located below arch/${ARCH}/${BOARD} – a common place for code like that is arch/${ARCH}/${BOARD}/setup.c.

This project however seemed to have raised some interest and I got asked quite a few times about the board specific changes I made – so here they are now:
the kernel patches which provide SPI buses on both boards, including GPIO mappings.

Since both targets I used the rfm12 module and driver on are running OpenWrt, I created both patches against the Linux vanilla tree having OpenWrt specific kernel patches already applied.

Changes however are small and clear, so they should be easy to understand and adapt.

The wiring I used to get the rfm12 module working on the NanoNote working by the way is the following:

GPIO | PIN on SD port | PIN on module | purpose / description
=====|================|===============|=================================
108  | D12 (1)        | MISO / SDO    | SPI: master input slave output
109  | D13 (2)        | nIRQ          | interrupt
104  | D08 (3)        | (unused)      | (unused)
X    | VDD (4)        | VDD           | power
105  | D09 (5)        | MOSI / SDI    | SPI: master output slave input
X    | VSS (6)        | GND (1+2)     | ground
106  | D10 (7)        | SCK           | SPI: clock
107  | D11 (8)        | nSEL          | SPI: chip select

There needs to be a resistor (10-100kOhm) between pin FSK (if used) of
the rfm12 module and VDD as pullup – however when just using ASK it isn’t needed anyway.

GDB behaves strange while debugging threads

While debugging issues involving binaries on a system running Linux, having a debugger such as GDB available is quite helpful.

However while working on a certain project we recently experienced quite some issues debugging applications involving threads.

Debugging the application on my local workstation worked quite fine, however on OpenWrt-targets – ARM as well as MIPS – it behaved rather strange: stack corruptions, missing traces, weird signals got issued…

After quite some time of debugging the debug issue, we found out the issue is caused by a stripped version of libpthread.so.

Stripped – not in the sense of a more lightweight but compatible version of the pthread library – but stripped by the utility “strip”, which purges all debug- and “other unneeded” symbols out of binaries to reduce their size, which usually is applied on all binaries by the OpenWrt framework automatically.

Usually binaries stripped by “strip” are still fully-fledged binaries, still usable with GDB (however without debugging symbols available of course). Applying strip on libpthread.so* however, it seems to strip out also stuff needed by GDB following and tracing threads. Without these symbols / meta-information not needed for running the actual application, but for tracking its threads, GDB results in mentioned issues above.

One might ask why someone is debugging binaries without debug symbols compiled in – reasons are obvious:

To check whether an object got stripped or not is quite easy using the “file” util:

$ file build_dir/target-arm_v5te_uClibc-0.9.30.1_eabi/root-foo/lib/libpthread-0.9.30.1.so
build_dir/target-arm_v5te_uClibc-0.9.30.1_eabi/root-foo/lib/libpthread-0.9.30.1.so: ELF 32-bit LSB shared object, ARM, version 1 (SYSV), dynamically linked (uses shared libs), stripped

$ file staging_dir/target-arm_v5te_uClibc-0.9.30.1_eabi/root-foo/lib/libpthread-0.9.30.1.so
staging_dir/target-arm_v5te_uClibc-0.9.30.1_eabi/root-foo/lib/libpthread-0.9.30.1.so: ELF 32-bit LSB shared object, ARM, version 1 (SYSV), dynamically linked (uses shared libs), not stripped

Long story short: When debugging applications involving threads, always use a non-stripped version of libpthread.so, even if debug symbols are not needed!

Ben NanoNote able to control radio power sockets

The Ben NanoNote is now able to switch radio controlled power sockets, too!

The rfm12 433MHz module, produced by HopeRF,  is attached to the microSD port of the Ben NanoNote, which pins are exposed via an microSD card dummy adapter.

rfm12 module attached to a microSD dummy

The System-on-a-chip used inside the Ben NanoNote (ingenic JZ47XX) allows us to put the microSD pins into GPIO mode, so we can (as already done for the first device, the Netgear WGT634u router, I connected an rfm12-module to) create and export an SPI bus on top of them to be able communicating with the module.

That way there’s no need of opening the device and/or soldering anything anywhere – the module is attached directly to the microSD dummy which gets simply inserted into microSD slot of the NanoNote.

rfm12 module attached to NanoNote running ncurses UI for switching power sockets

I wrote a basic but fully working ncurses frontend using the rfm12 library listing configured devices waiting for getting switched.

There’s also a ready-to-use XMLRPC daemon available which exposes all configured devices and provides functions for controlling them, so UIs for controlling devices are not limited to run on the same system the rfm12 module is installed on.

ncurses UI for switching configured radio controlled power sockets on the Ben NanoNote

I’ve also written a little GUI in python using the qt4 toolkit, connecting to the master via XML-RPC:

switching radio controlled power via a GUI using pyqt4

Several other frontends are work-in-progress as e.g. a GUI for the Android platform, as well as one based on qt4/QML being able to run e.g. on phones running Meego/Maemo as operating system – both using the XML-RPC interface.

So all major parts of the project are mostly finished now and the API is more or less fix.

The the whole project now consists of (a rough overview):

  1. the kernel module which communicates with the actual hardware (so the rfm12 module) and exposes a character device to userspace
  2. the rfm12 library which
    • connects to the kernel module
    • contains the device type specific data and code to modulate signals which control the actual power sockets
    • provides functions for reading / writing configuration files and controlling / switching devices
  3. applications using the library and its functions for actual controlling of devices, which could be / already are:
    • UI applications linked directly against librfm12 (an ncurses frontend (shown above) is available yet)
    • daemons providing network interfaces (a daemon exporting functionality via XMLRPC is available yet , one doing the same but using JSON-RPC as underlying rpc method is going to be implemented soon)
  4. UIs running on different machines, using these RPC services  (e.g. above pyqt4  frontend; android- and qml-frontends are work-in-progress)

Devices are getting configured via configuration files, describing the product type of the device, a name and the actual code which is used to identify devices of a certain product type group.

The config used by the applications shown on the photos / screenshots above just looks this:

[socket_A]
label = “one”
product = “P801B”
code = “1111110000″
[socket_B]
label = “two”
product = “2272″
code = “1111110000″
[socket_C]
label = “three”
product = “2272″
code = “1111101000″

One of the tasks I’m working on right now, is state sharing. While the list of configured devices and it’s states (on/off) is already shared among all XML-RPC clients (so having switched a unit in one client, others will fetch the changed state next time they poll/refresh), the state is not yet shared between several processes invoking the librfm12.

Issue is: Every process linked against librfm12 creates its own list of devices, including states – so every process has its own copy. Changes done in one process are not shared among others. This could be solved using IPC (System V shared memory, sockets every instance connects to, etc.).

That’s it – feedback and/or participation is highly appreciated!


Ben NanoNote having an rfm12 module attached via microSD-port and several types of radio controlled power sockets

Source Code is still available on github: https://github.com/mirko/rfm12-ASK-for-linux :)

RFM12 under Linux and remote controlled power sockets

Currently I’m working on a project communicating and transmitting signals over the air with an 433 MHz radio module called “rfm12“, produced by HopeRF, soldered onto devices capable of running OpenWrt and having at least 3 accessible GPIO’s.

Short story long:

These radio modules are capable of sending / receiving over the ISM frequency band, as e.g. 433 MHz or 868 MHz and just cost about 5 Euros.

RFM12 module

RFM12 module soldered onto eval board

The idea was to get the module working on several embedded boards running Linux, e.g. routers, microcomputers such as the NanoNote, etc. via a generic software interface.

The rfm12 module is controlled via the 4-wire protocol SPI which basically is based on toggling pins between the machine’s logic-levels (high/low) at an individual non-specified clock-speed (http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus).

Since most of mentioned boards do not own a native SPI bus, but several GPIO’s (most LED’s are connected via GPIO’s on such devices), SPI can be “emulated” by toggling these GPIO’s in a specific way (also called “bitbanging“).

That way there’s no need for any other electronic peripherals such as microcontrollers, semiconductors, resistors, etc. – the chip is directly connected with the board – everything is done in software.

Inspired by the project “ethersex” – a project programming and maintaining a software for Atmel AVR micro-controllers used for home- / building automation – and an approach of soldering the module onto a specific router, communicating via SPI over GPIO’s (however used code is rather old, unmaintained and board-specific)  – the idea came up to write a generic linux kernel module to support the module from within linux directly.

Based on the ideas realised with the ethersex project, I decided to aim my project on being able to switch remote controlled power sockets of which I own several (to each other incompatible) modules.

Because the rfm12 module is (only) capable of doing FM (modulating payload data on top of the frequency), but lot’s of devices are controlled via AM (most remote controlled power sockets included), we emulate AM by simply turning the module on and off in a specific sequence.

Since this operation is timing critical and needs to be atomic, we need to do basic stuff in the kernel space rather than from userspace.

The whole project is going to consist of 4 major parts:

My testing device is an old Netgear WGT634U I had in spare which has a broadcom 47xx SoC working in and 4 unused GPIO’s available.

RFM12 module directly connected to a Netgear WGT634U router

Implemented yet is support for the most common radio controlled sockets sold – the ones which have a 2272/2262 IC built in (including these Chinese versions which get on fire – http://ec.europa.eu/consumers/dyna/rapex/create_rapex.cfm?rx_id=142 #25) and the ones using an P801B chip.

radio controlled power sockets: 2272, P801B, 2262

I also have a set of radio controlled dimmers which protocol I’m going to implement soon…

For now the source code is hosted on github: https://github.com/mirko/rfm12-ASK-for-linux – there’s no project site yet but will be created if the project is growing / interest is getting raised :)

UPDATE: In case you’re willing to participate, you’re more than welcome! Just drop me an email… There’s lot’s of stuff I’d like to see implemented, especially usable (G)UI’s… but for sure it’s not just about me: patches, feedback, enhancements and feature-requests (in a certain extent) are highly appreciated!

closing…

Being back home for almost two month now, I finally find some time to close this category, my trip to Bali.

I’ve been in Tanah Lot – an area where a rather famous temple of the same denominator is located. It’s kind of an island during high tide but accessible when tide is low.

Because of it’s formation, location and a spring of freshwater inside, a priest declared it as an holy place in the 15th century.

Seriously, it’s an amazing place (however flooded by tourists and locals trying to sell stuff).

After Tanah Lot I got back to Sanur, wanted to stay there just a few days and then move to the so called Gili islands…

…however unfortunately I got ill, got the Dengue fever.

I don’t want to elaborate my almost last 10 days on Bali, however it was everything but nice and I do not wish anyone getting this bloody fever – seriously…

Closing statement:

It was great (apart from the fever I got)!

Seriously, Bali is no place where you’re going to struggle in any way… the Balinese economy is based on tourism, so you can get there almost every (western) stuff – it’s everything but a survival training (assumed you’re not getting ill).

Bali is a perfect mix of paradise-like beach and sea (have a look at the photos posted a few posts below) and cultural experiences (despite the tourism the Balinese people try hard to keep and practise their culture) like their huge amount of temples, sacrificial offerings several times a day, performances, etc.

There is lot’s of tourism, and partially too much of it for sure (for example Kuta and surroundings) – however the locals are really lovely and open-minded, it’s quite easy to socialise and get in touch with them…

Sharing some time of their everyday life is a definite recommendation if you’re not just there for beach, sea and sun but interested as well in their daily grind and culture.

They are more than pleased to show you around, quiet interested in western politics, habits, views, etc. – answering your questions in exchange for yours :)

To those Balinese / Indonesian I met there, reading this:

Thanks you so much for the great time !!

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